1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a semiconductor integrated circuit having memory cell arrays arranged in a matrix form.
2. Description of the Related Art
To respond to requests for a decrease in a breakdown voltage of a gate oxide film and lower power consumption by micro-fabricating a transistor structure, a power source voltage (operation voltage) of a semiconductor integrated circuit has recently become low. A transistor operates at a higher speed, in proportion as an effective gate voltage which is a value obtained by subtracting its threshold voltage from its operation voltage is higher. However, since the threshold voltage of the transistor is little dependent on the power source voltage, the effective gate voltage of the transistor becomes low according to a decrease in the power source voltage. Consequently, an operation speed of the transistor is made slower in proportion as the power source voltage is lower.
To maintain the high-speed operation of the transistor, the effective gate voltage of the transistor needs to be maintained by decreasing its threshold voltage in accordance with a drop of the power source voltage. Meanwhile, as the threshold voltage of the transistor becomes lower, a sub-threshold leak current, which flows between a drain and a source of the transistor even if a gate-source voltage of the transistor is made to equal to 0 V, increases. Therefore, if the threshold voltage of the transistor is dropped to maintain its high-speed operation, a standby current of the semiconductor integrated circuit increases.
A technology is disclosed in Japanese Unexamined Patent Application Publication No. Hei 5(1993)-210976, in which a switching transistor is disposed between a power supply line and a source electrode of a transistor to decrease a standby current. Even when a threshold voltage of the transistor is decreased, this technology prevents the standby current from being increased by turning off the switching transistor during a standby state.
However, since the switching transistor acts as a load on the power supply line when an internal circuit of a semiconductor integrated circuit operates, there has been a problem that the arrangement of the switching transistor decreases an operation speed of the circuit. It is possible to prevent a decrease in the operation speed of the circuit by making a size of the switching transistor large. However, in this case, because a sub-threshold leak current of the switching transistor increases, the standby current increases. Accordingly, when the switching transistor is arranged between the circuit and the power supply line, it has been difficult to satisfy both of the operation speed of the circuit and the standby current.
In Japanese Unexamined Patent Application Publication No. Hei 8(1996)-321763, a technology is disclosed, in which by applying a voltage different from a power source voltage to a gate of a switching transistor, an internal circuit is allowed to operate at a high speed and an increase in a standby current is controlled. In this technology, a gate-source voltage of the switching transistor is made to be high during an operation of the internal circuit, whereby a capability to supply a current to the internal circuit is enhanced. The gate-source voltage of the switching transistor is made to be negative during the standby of the internal circuit, whereby a cutoff characteristic is improved.
However, in order to set the gate-source voltage of the switching transistor to a voltage different from the power source voltage, a voltage generating circuit (a high voltage generating circuit, a negative voltage generating circuit or the like) is necessary. Therefore, there has been a problem that an extra current is consumed by the voltage generating circuit and the standby current cannot be decreased as the whole semiconductor integrated circuit even when the cutoff characteristic during the standby state is improved. Moreover, since amplitude of a gate voltage of the switching transistor becomes large, a charge and discharge current for a gate capacitance increases. Accordingly, when a change between an active state and a standby state is often made, there has been a problem that consumption current increase.
An object of the present invention is to provide a semiconductor integrated circuit capable of decreasing current consumption during a standby state of the semiconductor integrated circuit without lowering the operation speed of the circuit.
According to one of the aspects of the present invention, a semiconductor integrated circuit has a plurality of switching transistors which connect power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. The power supply terminals of the first circuit blocks operating at different timings among the first circuit blocks are connected to each other by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Therefore, when a certain first circuit block operates, a power source current is supplied to the first circuit block via the plurality of switching transistors. Since a total size of the switching transistors for the first circuit block in operation can be made large, a power source resistance (or a ground resistance) of a power source connected to the first circuit block can be decreased and an operation speed of the first circuit block can be increased compared to that of conventional art.
Since the plurality of switching transistors can be shared among the first circuit blocks which do not operate simultaneously, the total size of the switching transistors can be made smaller compared to a case where the switching transistors are arranged for each of the first circuit blocks. As a result, an increase in a total sum of sub-threshold currents of the switching transistors can be prevented when the first circuit blocks do not operate, and a current when the first circuit blocks do not operate (standby current) can be decreased. Furthermore, since the switching transistors can be shared among the first circuit blocks which do not operate simultaneously, each chip size can be made small.
Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current. Particularly, in a semiconductor integrated circuit constituting the first circuit blocks including internal transistors with decreased threshold voltages, both the operation speed and the standby current can be satisfied.
According to another aspect of the present invention, threshold voltages of the switching transistors are set to be higher than those of internal transistors included in the first circuit blocks. Since the plurality of switching transistors are connected to each other in parallel, even when the threshold voltages of the switching transistors are made higher and the sub-threshold leak current is further decreased, drivability of the switching transistors can be made equal to those before the threshold voltages thereof are made higher, by only making sizes of the respective switching transistors a little larger. More specifically, an increase in the chip size can be suppressed to the minimum, and the sub-threshold leak current can be further decreased.
According to another aspect of the present invention, source electrodes of the internal transistors turned off during a standby state of the semiconductor integrated circuit in each of the first circuit blocks are connected to the power supply line via the internal power supply line and the switching transistors. The switching transistors are connected only to such internal transistors as necessary for decreasing the standby current and the other internal transistors are directly connected to the power supply line, whereby the first circuit blocks can be operated at a higher speed and logic of the circuits can be determined even when the semiconductor integrated circuit is under the standby state.
According to another aspect of the present invention, the switching transistors and the first circuit blocks are dispersedly arranged. For example, a semiconductor integrated circuit capable of satisfying both an operation speed and a standby current without increasing the chip size can be constituted by arranging the switching transistors and the first circuit blocks, taking advantage of empty areas where no devices are formed.
According to another aspect of the present invention, the switching transistors and the first circuit blocks are arranged in a matrix form with intervals in between. The internal power supply line connects to each other the power supply terminals of the part of the first circuit blocks, the connection done along a line with a smaller number of first circuit blocks operating simultaneously. Therefore, the number of the switching transistors for the first circuit blocks in operation can be increased, and a current supply capability per first circuit block can be enhanced. As a result, the first circuit blocks can be operated at a high speed.
According to another aspect of the present invention, a plurality of rectangular memory cell arrays is arranged in a matrix form with intervals in between. Each memory cell array has memory cells each connected to a word line and a bit line. For example, the semiconductor integrated circuit is constituted as a semiconductor memory or a system LSI including a semiconductor memory. In areas adjacent to four corners of the memory cell arrays, the switching transistors and the first circuit blocks are arranged. In each first circuit block, array control circuits for controlling the memory cell arrays are formed. The internal power supply line connects power supply terminals of the array control circuits to each other, which are aligned in wiring directions of the word line or the bit line. Generally, when data is read/written from/to the semiconductor memory, a part of the array control circuits operates, and only a predetermined memory cell array is selected in response to an address signal. At this time, the other part of array control circuits and the other memory cell arrays do not operate. Therefore, by connecting the array control circuits which operate at different timings (that is, do not operate simultaneously) to each other, by the internal power supply line, the number of the switching transistors to the array control circuits in operation can be increased and a current supply capability per array control circuit can be enhanced. As a result, the array control circuits can be operated at a high speed and access time of the semiconductor memory can be shortened.
According to another aspect of the present invention, column control circuits (the array control circuits) for inputting/outputting data transmitted to the bit line are connected by the internal power supply line. By connecting the column control circuits operating at different timings to each other, by the internal power supply line, the number of the switching transistors to the column control circuits in operation can be increased and a current supply capability per column control circuit can be enhanced. As a result, the column control circuits can be operated at a high speed and column operation time of the semiconductor memory can be shortened.
According to another aspect of the present invention, row control circuits (the array control circuits) for selecting the word line are connected by the internal power supply line. By connecting the row control circuits operating at different timings to each other, by the internal power supply line, the number of the switching transistors to the row control circuits in operation can be increased and a current supply capability per row control circuit can be enhanced. As a result, the row control circuits can be operated at a high speed and a row operation time of the semiconductor memory can be shortened.
According to another aspect of the present invention, a column control circuit for inputting/outputting data transmitted to the bit line and a row control circuit for selecting the word line are connected to each other by the internal power supply line. Generally, when data is read/written from/to a semiconductor memory, the row control circuits operate first, then the column control circuits operate. More specifically, the row control circuits and the column control circuits operate at different timings from each other. Therefore, the number of the switching transistors to the row control circuits and the column control circuits in operation can be increased. Accordingly, the row control circuits and the column control circuits can be operated at a high speed and access time of the semiconductor memory can be shortened.
According to another aspect of the present invention, a read control circuit operating during a read operation and a write control circuit operating during a write operation are connected by the internal power supply line. The read operation and the write operation never occur simultaneously. More specifically, the read control circuits and the write control circuits always operate at different timings from each other. Since the number of the switching transistors for the read control circuits and the write control circuits in operation can be increased, the read control circuits and the write control circuits can be operated at a high speed. As a result, read and write operation times of the semiconductor memory can be shortened.
According to another aspect of the present invention, second circuit blocks which operate at different timings from the first circuit blocks are respectively arranged between the first circuit blocks connected by the internal power supply line. Power supply lines of the second circuit blocks are connected to the internal power supply line. By connecting to each other the first/second circuit blocks operating at different timings by the internal power supply line, the number of the switching transistors for the first/second circuit blocks in operation can be increased, and a current supply capability per first/second circuit block can be enhanced. As a result, the first/second circuit blocks can be operated at a high speed.
According to another aspect of the present invention, source electrodes of the internal transistors turned off during a standby state of the semiconductor integrated circuit in each of the second circuit blocks are connected to the power supply line via the internal power supply line and the switching transistors. The switching transistors are connected only to such internal transistors as necessary for decreasing the standby current and the other internal transistors are directly connected to the power supply line, whereby the second circuit blocks can be operated at a higher speed and a logic of the circuits can be determined even when the semiconductor integrated circuit is under the standby state.
According to another aspect of the present invention, the second circuit blocks operate at different timings from each other. By connecting the second circuit blocks operating at different timings to each other by the internal power supply line, the number of the switching transistors to the second circuit blocks in operation can be increased and a current supply capability per second circuit block can be enhanced. As a result, the second circuit blocks can be operated at a high speed.
According to another aspect of the present invention, a plurality of memory cell arrays is provided, each having memory cells each connected to a word line and a bit line. For example, a semiconductor integrated circuit is constituted as a semiconductor memory or a system LSI including a semiconductor memory. Column control circuits (the first circuit blocks) for inputting/outputting data transmitted to the bit line and row control circuits (the second circuit blocks) for selecting the word line are connected to each other by the internal power supply line. Generally, when data is read/written from/to the semiconductor memory, the row control circuits operate first, then the column control circuits operate. More specifically, the row control circuits and the column control circuits operate at different timings from each other. Therefore, the number of the switching transistors for the row control circuits or the column control circuits in operation can be increased. Accordingly, the row control circuits and the column control circuits can be operated at a high speed, and access time of the semiconductor memory can be shortened.